----------------------------------------------------------------------------------
— test bench for cir1
------------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cir1test is
--  Port ( );
end cir1test;

architecture Behavioral of cir1test is

  component cir1
    port (a: in STD_LOGIC;
          b, c: out STD_LOGIC);
  end component;

signal a, b, c : STD_LOGIC;
begin

U1: cir1 port map (a, b, c);

process
begin
   a <= '1';
   wait for 10ns;
   a <= '0';
   wait for 50ns;
   a <= '1';
   wait;

end process;

end Behavioral;