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-- 4-bit adder
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder4 is
  Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0);
         cin : in STD_LOGIC;
         s : out STD_LOGIC_VECTOR (3 downto 0);
         co : out STD_LOGIC);
end adder4;

architecture Behavioral of adder4 is

component bit_adder
  port (a, b, cin: in STD_LOGIC;
        cout, sum: out STD_LOGIC);
end component;

signal c : STD_LOGIC_VECTOR (3 downto 1);

begin

FA0: bit_adder port map (a(0), b(0), cin, c(1), s(0));
FA1: bit_adder port map (a(1), b(1), c(1), c(2), s(1));
FA2: bit_adder port map (a(2), b(2), c(2), c(3), s(2));
FA3: bit_adder port map (a(3), b(3), c(3), co, s(3));

end Behavioral;