----------------------------------------------------------------------------------
-- full adder
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cir3_2 is
  Port ( a, b, cin: in unsigned (0 downto 0);
         sel : in STD_LOGIC;
         cout, sum: out STD_LOGIC);
end cir3_2;

architecture Behavioral of cir3_2 is

signal temp : unsigned (1 downto 0);

begin

temp <= '0'&a + b + cin;

sum <= temp(0) when sel = '0' else '0'; -- conditional signal assignment

with sel select
cout <= temp(1) when '0',
        '0'     when others; -- selected signal assignment

end Behavioral;