----------------------------------------------------------------------------------
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cir3_2test is
--  Port ( );
end cir3_2test;

architecture Behavioral of cir3_2test is

    COMPONENT cir3_2
      Port ( a, b, cin : in unsigned;
             sel : in STD_LOGIC;
             cout, sum : out STD_LOGIC);
    END COMPONENT;
    
signal cout, sum, sel : STD_LOGIC;
signal a, b, cin : unsigned (0 downto 0);

begin

U1: cir3_2 port map (a, b, cin, sel, cout, sum);

process 
begin

a <= "1";
b <= "1";
cin <= "1";
sel <= '0';
wait for 10ns;
sel <= '1';
wait for 10ns;
a <= "0";
b <= "1";
cin <= "0";
sel <= '0';
wait for 10ns;
sel <= '1';
wait for 10ns;
a <= "1";
b <= "1";
cin <= "0";
wait for 10ns;
sel <= '0';
wait;

end process;

end Behavioral;