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-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cir4_1test is
--  Port ( );
end cir4_1test;

architecture Behavioral of cir4_1test is

    COMPONENT adder4
      Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0);
             cin : in STD_LOGIC;
             s : out STD_LOGIC_VECTOR (3 downto 0);
             co : out STD_LOGIC);
    END COMPONENT;
    
signal cin, co: STD_LOGIC;
signal a, b, s: STD_LOGIC_VECTOR (3 downto 0);

begin

U1: adder4 port map (a, b, cin, s, co);

process 
begin

a <= "1111";
b <= "0001";
cin <= '1';
wait for 10ns;
a <= "0101";
b <= "1110";
cin <= '0';
wait for 10ns;
a <= "0011";
b <= "0101";
cin <= '0';
wait for 10ns;
wait;

end process;

end Behavioral;