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-- D flip flop with synchronous reset
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library IEEE;
use IEEE.NUMERIC_BIT.ALL;

--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff_resettable is
  Port ( d, clk, reset : in bit;
         q : out bit);
end dff_resettable;

architecture Behavioral of dff_resettable is

begin

 process (clk, reset)
 begin
  if clk'event and clk='1' then 
   if (reset='1') then q <= '0'; -- synchronous reset
   else q <= d;                  -- capture d into the flip flop on rising edge of clock
   end if;
  end if;
 end process;

end Behavioral;