---------------------------------------------------------------------------------- -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.NUMERIC_BIT.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity cir5_1test is -- Port ( ); end cir5_1test; architecture Behavioral of cir5_1test is COMPONENT counter5 port ( clk, reset : in bit; q : out unsigned (4 downto 0)); END COMPONENT; signal clk, reset : bit; signal q : unsigned (4 downto 0); begin U1: counter5 port map (clk, reset, q); clk <= not clk after 5ns; process begin reset <= '1'; wait for 10ns; reset <= '0'; wait for 200ns; reset <= '1'; wait for 30ns; reset <= '0'; end process; end Behavioral;