---------------------------------------------------------------------------------- -- sim_example1 ---------------------------------------------------------------------------------- library IEEE; use IEEE.NUMERIC_BIT.ALL; --use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sim_example is Port ( a, b : inout bit); end sim_example; architecture Behavioral of sim_example is begin p1:process (b) begin a <= '1'; a <= transport '0' after 5ns; end process p1; p2:process (a) begin if a = '1' then b <= not b after 10ns; end if; end process p2; end Behavioral;