----------------------------------------------------------------------------------
-- arrays
----------------------------------------------------------------------------------


library IEEE;
use IEEE.NUMERIC_BIT.ALL;

--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity parity_gen is
  Port ( x : in unsigned (3 downto 0);
         y : out unsigned (4 downto 0));
end parity_gen;

architecture Behavioral of parity_gen is

signal paritybit : bit;

type outTable is array(0 to 15) of bit;

constant OT:outTable :=('1','0','0','1','0','1','1','0',
                        '0','1','1','0','1','0','0','1');

begin

 paritybit <= OT(to_integer(x));
 y <= x & paritybit;
 
end Behavioral;