----------------------------------------------------------------------------------
— this circuit has a static-1 hazard
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cir1 is
  Port (a: in STD_LOGIC;
        b, c: out STD_LOGIC);
end cir1;

architecture Behavioral of cir1 is

signal temp1, temp: STD_LOGIC;

begin

temp1 <= not a after 5ns;
temp <= temp1 or a;

b <= temp1;
c <= temp;

end Behavioral;