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-- 
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library IEEE;
use IEEE.NUMERIC_BIT.ALL;

--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cir4_4test is
--  Port ( );
end cir4_4test;

architecture Behavioral of cir4_4test is

    COMPONENT dff_resettable
      Port ( d, clk, reset : in bit;
             q : out bit);
    END COMPONENT;
    
signal clk, reset, d, q : bit;

begin

U1: dff_resettable port map (d, clk, reset, q);

clk <= not clk after 5ns;

process 
begin

d <= '1';
reset <= '1';
wait for 10ns;
d <= '1';
reset <= '0';
wait for 10ns;
d <= '0';
reset <= '0';
wait for 10ns;
d <= '1';
reset <= '0';
wait for 10ns;
d <= '1';
reset <= '1';
wait for 10ns;
d <= '1';
reset <= '0';
wait;

end process;

end Behavioral;