---------------------------------------------------------------------------------- -- 5-bit counter with async reset ---------------------------------------------------------------------------------- library IEEE; use IEEE.NUMERIC_BIT.ALL; --use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter5 is Port ( clk, reset : in bit; q : out unsigned (4 downto 0)); end counter5; architecture Behavioral of counter5 is signal count : unsigned (4 downto 0); begin process (clk, reset) begin if reset='1' then count <= "00000"; --async reset elsif clk'event and clk='1' then --pos esge of clk if count = "10001" then count <= "00000"; --terminal count is 17 else count <= count + 1; end if; end if; end process; q <= count; end Behavioral;