----------------------------------------------------------------------------------
-- sim_example1
----------------------------------------------------------------------------------


library IEEE;
use IEEE.NUMERIC_BIT.ALL;

--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sim_example is
  Port ( a, b, c, d : inout unsigned (3 downto 0);
         e : in bit);
end sim_example;

architecture Behavioral of sim_example is

begin

 p1:process
  begin
   wait on e;
   a <= "0001" after 5ns;
   b <= a + "0001";
   c <= b after 10ns;
   wait for 0ns;
   d <= b after 3ns;
   a <= a + "0101" after 15ns;
   b <= b + "0111";
 end process p1;

end Behavioral;