---------------------------------------------------------------------------------- -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.NUMERIC_BIT.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity cir6_2test is -- Port ( ); end cir6_2test; architecture Behavioral of cir6_2test is COMPONENT sim_example port ( a, b, c, d : inout unsigned (3 downto 0); e : in bit); END COMPONENT; signal a, b, c, d : unsigned (3 downto 0); signal e : bit; begin U1: sim_example port map (a, b, c, d, e); process begin wait for 20ns; e <= '1'; wait; end process; end Behavioral;