---------------------------------------------------------------------------------- -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.NUMERIC_BIT.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity cir7_1test is -- Port ( ); end cir7_1test; architecture Behavioral of cir7_1test is COMPONENT parity_gen port ( x : in unsigned (3 downto 0); y : out unsigned (4 downto 0)); END COMPONENT; signal x : unsigned (3 downto 0); signal y : unsigned (4 downto 0); begin U1: parity_gen port map (x, y); process begin wait for 30ns; x <= "0001"; wait for 10ns; x <= "0101"; wait for 10ns; x <= "1101"; wait for 10ns; wait; end process; end Behavioral;