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-- 
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library IEEE;
use IEEE.NUMERIC_BIT.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cir7_2test is
--  Port ( );
end cir7_2test;

architecture Behavioral of cir7_2test is

    COMPONENT mat_access
      port ( clk, reset : in bit;
             y, c_out : out integer);
    END COMPONENT;
   
signal clk, reset : bit; 
signal c_out, y : integer;

begin

U1: mat_access port map (clk, reset, y, c_out);

clk <= not clk after 5ns;

process 
begin

reset <= '1';
wait for 10ns;
reset <= '0';
wait for 200ns;
reset <= '1';
wait for 100ns;
reset <= '0';

end process;

end Behavioral;