----------------------------------------------------------------------------------
-- test bench to be simulated with adder4 design from cir4-2.vhd
----------------------------------------------------------------------------------


library IEEE;
use IEEE.NUMERIC_BIT.ALL;

--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cir8_1test is
--  Port ( );
end cir8_1test;

architecture Behavioral of cir8_1test is

    COMPONENT adder4
      Port ( a, b : in unsigned (3 downto 0);
             cin : in bit;
             s : out unsigned (3 downto 0);
             co : out bit);
    END COMPONENT;
    
signal cin, co: bit;
signal a, b, s: unsigned (3 downto 0);

constant N : integer := 11;
type bv_arr is array (1 to N) of unsigned (3 downto 0);
type bit_arr is array (1 to N) of bit;

constant addend_array : bv_arr := ("0111", "1101", "0101", "1101", "0111", "1000", "0111", "1000", "0000", "1111", "0000");
constant augend_array : bv_arr := ("0101", "0101", "1101", "1101", "0111", "0111", "1000", "1000", "1101", "1111", "0000");
constant cin_array    : bit_arr := ('0', '0', '0', '0', '1', '0', '0', '0', '1', '1', '0');

constant sum_array    : bv_arr := ("1100", "0010", "0010", "1010", "1111", "1111", "1111", "0000", "1110", "1111", "0000");
constant cout_array   : bit_arr := ('0', '1', '1', '1', '0', '0', '0', '1', '0', '1', '0');

begin

U1: adder4 port map (a, b, cin, s, co);

process 
begin
 for i in 1 to N loop
  a <= addend_array(i);
  b <= augend_array(i);
  cin <= cin_array(i);
  wait for 40ns;
  assert (s = sum_array(i) and co = cout_array(i))
   report "Wrong Answer"
    severity error;
 end loop;
 report "Test Finished";
end process;

end Behavioral;