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-- ECE 3401 Spring 2018: Mealy state machine (1-process type implementation)
-- detects sequence 101 and asserts output when it is coincident with the last 1 in 101 
-- University of Connecticut
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity cir9_1 is
port(
	clk, reset, x : in std_logic;
	z             : out std_logic);
end cir9_1;

architecture Behavioral of cir9_1 is

signal state : integer range 0 to 2;
	
begin

process( clk, reset )
begin
 if ( reset = '1' ) then state <= 0; -- asynchronous reset
 elsif (rising_edge(clk)) then
  case state is -- decode next state
   when 0 => if x='0' then state <= 0; else state <= 1; end if;
   when 1 => if x='0' then state <= 2; else state <= 1; end if;
   when 2 => if x='0' then state <= 0; else state <= 1; end if;
   when others => null; -- should never occur!
  end case;
 end if;
end process;

z <= '1' when (state = 2 and x = '1') else '0';

end Behavioral;