Welcome to ECE 3401/ CSE 3302 - Digital Systems Design

Course Syllabus

Instructor

• Omer Khan
• Office: ITEB 447
• Email: khan@uconn.edu
• Office Hours: Online via WebEx or Teams preferably during 11am-Noon on Tue/Thu (make appointment via email)

TAs

• Abdul Rasheed Sahni and Salman Khaliq
• Email: abdul.rasheed@uconn.edu, salman.abdul_khaliq@uconn.edu
• Office Hours: M/W/F 4-5pm for signup slots (Online via WebEx or Teams)

Announcements

• Exam 3 is scheduled in-person, in-class on April 6, 2021 (lectures 13 through 20 inclusive)
• Exam 2 is scheduled in-person, in-class on March 11, 2021 (lectures 7 through 13 inclusive)
• Exam 1 is scheduled in-person, in-class on Feb 16, 2021 (lectures 1 through 7 inclusive)
• Exams are strictly in person. For any exceptions to be considered, a student being quarantined should contact the Dean of Students, who must send official accommodation request to the instructor before an exam. Here is the FAQ from CETL.
• Class lectures may be livestreamed via WebEx. Students are encouraged to attend the classes in person. Attendance of in person participation will be taken regularly.
• TA help hours are Mon/Wed/Fri 4-5pm EST. You can signup using Google Form.

Lectures

• Lecture 1: Introduction to Logic Design and Hardware Descriptive Languages - PDF (textbook reading: 1.1 - 1.3) Video recording
• Lecture 2: Combinatorial Logic and VHDL - PDF (textbook reading: 1.4 - 1.5 and 2.1 - 2.4) Video recording (VHDL example: cir1.vhd, cir1test.vhd)
• Lecture 3: VHDL Modules, Types, Operators, Libraries - PDF (textbook reading: 2.4, 2.12.1, 2.10.1) Video recording (VHDL examples: cir3_1.vhd, bit_adder.vhd, cir3_1test.vhd cir3_2.vhd, cir3_2test.vhd)
• Lecture 4: VHDL Operators, Libraries, and Introduction to Sequential Logic - PDF (textbook reading: 2.10.2, 2.13, 1.6, 2.5, 2.6) Video recording (VHDL examples: cir4_1.vhd, cir4_1test.vhd cir4_2.vhd, cir4_2test.vhd, cir4_3.vhd, cir4_3test.vhd, cir4_4.vhd, cir4_4test.vhd)
• Lecture 5: Sequential Logic Modeling and VHDL - PDF (textbook reading: 1.6, 2.5, 2.6, 2.7, 2.12.2, 2.9) Video recording (VHDL examples: cir5_1.vhd, cir5_1test.vhd)
• Lecture 6: VHDL Delay and Simulation - PDF (textbook reading: 2.12.2, 2.8, 2.9) Audio recording only (VHDL examples: cir6_1.vhd, cir6_1test.vhd, cir6_2.vhd, cir6_2test.vhd)
• Lecture 7: VHDL Simulation and Synthesis - PDF (textbook reading: 2.9, 2.11, 2.14) Video recording
• Lecture 8: VHDL Synthesis - PDF (textbook reading: 2.11, 2.14) Video recording
• Lecture 9: VHDL Array, Loop and Assert Constructs and Synchronous Finite State Machine Design - PDF (textbook reading: 2.16, 2.17, 2.18, 2.19, 1.7, 1.8) Video recording (VHDL examples: cir9_1.vhd, cir9_1test.vhd, cir9_2.vhd, cir9_2test.vhd, cir9_3test.vhd)
• Lecture 10: Synchronous Finite State Machine Design - PDF (textbook reading: 1.7, 1.8, 2.15.1) Video recording (VHDL examples: cir10_1.vhd, cir10_1test.vhd, cir10_2.vhd, cir10_2test.vhd)
• Lecture 11: Synchronous FSM/ Datapath Designs I - PDF (textbook reading: 1.7, 1.8, 2.15.1, 4.4) Video recording (VHDL examples: cir11_2.vhd, cir11_2test.vhd)
• Lecture 12: Synchronous FSM/ Datapath Designs II - PDF (textbook reading: 4.4, 4.3) Video recording
• Lecture 13: Datapath and State Machine Charts (SM Charts) - PDF (textbook reading: 4.8, 5.1, 5.3) Video recording
• Lecture 14: SM Charts and Microprogramming - PDF (textbook reading: 5.1, 5.3, 5.5) Video recording
• Lecture 15: Microprogramming - PDF (textbook reading: 5.3, 5.5) Video recording
• Lecture 16: Processor Design I - PDF (textbook reading: 9.1) Video recording
• Lecture 17: Processor Design II - PDF (textbook reading: 9.1, 9.2, 9.3) Video recording
• Lecture 18: Processor Design III - PDF (no textbook reading) Video recording
• Lecture 19: High-Level Synthesis (HLS) I - PDF (no textbook reading) Video recording
• Lecture 20: High-Level Synthesis (HLS) II - PDF (no textbook reading) Video recording
• Lecture 21: Processor Design and High Level Synthesis Wrap-up - PDF (no textbook reading), (HLS example: neuralnet.c, neuraltest.c) Video recording
• Lecture 22: Programmable Logic Devices - PDF (textbook reading: chapter 3) Video recording
• Lecture 23: Verilog HDL - PDF (no textbook reading)

Homeworks (due at HuskyCT specified deadline - no late submissions will be accepted)

• Homework 1: PDF, Solution PDF (due via HuskyCT on Jan 28, 2021)
• Homework 2: PDF, Solution PDF (due via HuskyCT on Feb 9, 2021)
• Homework 3: PDF, Solution PDF (due via HuskyCT on March 2, 2021)
• Homework 4: PDF, Solution PDF (due via HuskyCT on March 9, 2021)
• Homework 5: PDF, Solution PDF (due via HuskyCT on March 23, 2021)
• Homework 6: PDF, Solution PDF (due via HuskyCT on April 1, 2021)
• Homework 7: PDF (due via HuskyCT on April 27, 2021)

Programming Assignments (due at HuskyCT specified deadline - no late submissions will be accepted)

• NOTE: (1) Utilize the TA help hours, (2) Take a look at the VHDL Toolchain Guide PDF
• PA 0 (due Feb 2, 2021): Complete all steps for the toolchain setup and run the lab0 with test0 testbench. Upload a single PDF of your simulation output in HuskyCT submission portal. PA0 Guide PDF, lab0.vhd, test0.vhd
• PA 1 (due via HuskyCT on Feb 25, 2021): Design of an ALU Accumulator in VHDL PA1-Handout PDF, pa1s21.zip
• PA 2 (due via HuskyCT on Mar 25, 2021): ALU Commander PA2-Handout PDF, pa2s21.zip
• PA 3 (due via HuskyCT on April 20, 2021): 32-bit Carry Look-ahead Adder PA3-Handout PDF, pa3s21.zip
• PA 4 (due via HuskyCT on April 23, 2021 at 5pm EST): A Simple Microcontroller Design PA4-Handout PDF, pa4s21.zip