Welcome to ECE 3401 - Digital Systems Design

Electrical and Computer Engineering
University of Connecticut

Spring 2022

Tuesdays and Thursdays 12:30pm - 1:45pm, AUST 344
Starting Feb 1, 2022 all lectures will be in person

Course Syllabus

Instructor

Omer Khan
Office: ITEB 447
Email: khan@uconn.edu
Office Hours: Tue/Thu 11am-Noon (In-person or Online via WebEx; only for confirmed appointments via email)

TAs

Jared Nye
Email: jared.nye@uconn.edu
Office Hours: M/W/F -- 5:30-6:30pm in ITE 134

Announcements

Final Exam: Friday, May 6th: 3:30pm to 5:30pm in class

Exam 2 is scheduled in-person, in-class on April 12, 2022 (lectures 10 through 18 inclusive)

Exam 1 is scheduled in-person, in-class on March 3, 2022 (lectures 1 through 9 inclusive)

Exams are strictly in person. For any exceptions to be considered, a student being quarantined should contact the Dean of Students, who must send official accommodation request to the instructor before an exam. Here is the FAQ from CETL.

Lectures

Lecture 1: Introduction to Logic Design and Hardware Descriptive Languages - PDF (textbook reading: 1.1 - 1.5)

Lecture 2: Combinatorial Logic and VHDL - PDF (textbook reading: 2.1 - 2.4) (VHDL example: cir1.vhd, cir1test.vhd)

Lecture 3: VHDL Modules, Types, Operators, Libraries - PDF (textbook reading: 2.4, 2.12.1, 2.10.1) (VHDL examples: cir3_1.vhd, bit_adder.vhd, cir3_1test.vhd cir3_2.vhd, cir3_2test.vhd)

Lecture 4: VHDL Operators, Libraries, and Introduction to Sequential Logic - PDF (textbook reading: 2.10.2, 2.13, 1.6) (VHDL examples: cir4_1.vhd, cir4_1test.vhd cir4_2.vhd, cir4_2test.vhd, cir4_3.vhd, cir4_3test.vhd, cir4_4.vhd, cir4_4test.vhd)

Lecture 5: Sequential Logic Modeling and VHDL - PDF (textbook reading: 1.6, 2.5, 2.6, 2.7, 2.12.2, 2.9) (VHDL examples: cir5_1.vhd, cir5_1test.vhd)

Lecture 6: VHDL Delay and Simulation - PDF (textbook reading: 2.12.2, 2.8, 2.9) (VHDL examples: cir6_1.vhd, cir6_1test.vhd, cir6_2.vhd, cir6_2test.vhd)

Lecture 7: VHDL Synthesis - PDF (textbook reading: 2.9, 2.11) (VHDL examples: cir6_3.vhd, cir6_3test.vhd)

Lecture 8: VHDL Synthesis and Arrays, Loops, Asserts Constructs - PDF (textbook reading: 2.14, 2.16, 2.17, 2.18, 2.19) (VHDL examples: cir9_1.vhd, cir9_1test.vhd, cir9_2.vhd, cir9_2test.vhd, cir9_3test.vhd)

Lecture 9: Synchronous Finite State Machine Design - PDF (textbook reading: 1.7, 1.8, 2.15.1) (VHDL examples: cir10_1.vhd, cir10_1test.vhd, cir10_2.vhd, cir10_2test.vhd)

Lecture 10: Synchronous FSM Designs - PDF (textbook reading: 1.7, 1.8, 2.15.1) (VHDL examples: cir11_2.vhd, cir11_2test.vhd, also look at cir10_1 and cir10_2 from lecture 9)

Lecture 11: Synchronous Design Examples - PDF (textbook reading: 4.4, 4.3, 4.8)

Lecture 12: Synchronous Design Examples and Midterm 1 Review - Lecture 12 PDF, Midterm 1 Review PDF (textbook reading: 4.3.1, 4.8)

Lecture 13: Datapath and State Machine Charts (SM Charts) - PDF (textbook reading: 5.1, 5.3)

Lecture 14: SM Charts and Microprogramming - PDF (textbook reading: 5.3, 5.5)

Lecture 15: Microprogramming - PDF (textbook reading: 5.3, 5.5)

Lecture 16: Processor Design I - PDF (textbook reading: 9.1)

Lecture 17: Processor Design II - PDF (textbook reading: 9.1, 9.2, 9.3)

Lecture 18: Processor Design III - PDF (no textbook reading)

Midterm 2 Review - Midterm 2 Review PDF

Lecture 19: High-Level Synthesis (HLS) I - PDF (no textbook reading)

Lecture 20: High-Level Synthesis (HLS) II - PDF (no textbook reading), (HLS example: neuralnet.c, neuraltest.c)

Lecture 21: Programmable Logic Devices - PDF (textbook reading: chapter 3)

Lecture 22: Verilog HDL - PDF (no textbook reading)

Homeworks (due at HuskyCT specified deadline - no late submissions will be accepted)

Homework 1: PDF, Solution PDF (due via HuskyCT on Feb 1, 2022 11:59pm EST)

Homework 2: PDF Solution PDF (due via HuskyCT on Feb 10, 2022 11:59pm EST)

Homework 3: PDF Solution PDF (due via HuskyCT on Feb 24, 2022 11:59pm EST)

Homework 4: PDF Solution PDF (due via HuskyCT on March 21, 2022 11:59pm EST)

Homework 5: PDF Solution PDF (due via HuskyCT on March 31, 2022 11:59pm EST)

Homework 6: PDF Solution PDF (due via HuskyCT on April 22, 2022 11:59pm EST)

Programming Assignments (due at HuskyCT specified deadline - no late submissions will be accepted)

Adding signals to Waveform PDF

NOTE: (1) Utilize the TA help hours, (2) Take a look at the VHDL Toolchain Guide PDF

PA 0 (due Jan 27, 2022): Complete all steps for the toolchain setup and run the lab0 with test0 testbench. Upload a single PDF of your simulation output in HuskyCT submission portal. PA0 Guide PDF, lab0.vhd, test0.vhd

PA 1 (due via HuskyCT on extended deadline Feb 18, 2022): Design of Parallel ALU Accumulators PA1-Handout PDF (updated 11-Feb-2022), pa1s22.zip

PA 2 (due via HuskyCT on Mar 10, 2022): ALU Datapath Commander PA2-Handout PDF, pa2s22.zip

PA 3 (due via HuskyCT on April 5, 2022): 8-bit Unsigned Binary Divider in VHDL PA3-Handout PDF, pa3s22.zip

PA 4 (due via HuskyCT on April 27, 2022): 8-bit Unsigned Binary Divider using Single-Address Microporgramming in VHDL PA4-Handout PDF, pa4s22.zip