Welcome to ECE 3401 / CSE 3302 - Digital Systems Design

Electrical and Computer Engineering
University of Connecticut

Spring 2023

Tuesdays and Thursdays 12:30pm - 1:45pm, ITE 336

Course Syllabus

Instructor

Omer Khan
Office: ITEB 447
Email: khan@uconn.edu
Office Hours: Tue/Thu 11:30am-12:30pm

TAs

Zachary DiMeglio
Email: zachary.dimeglio@uconn.edu
Office Hours: Mon 3-5pm and Tue 2-4pm in E2 Room 305

Announcements

Final Exam is scheduled in ITE 336 from 3:30-5:30pm on May 5, 2023 (all lectures)

Exam 2 is scheduled in-person, in-class on April 20, 2023 (lectures 10 through 17 inclusive)

Exam 1 is scheduled in-person, in-class on Feb 23, 2023 (lectures 1 through 9 inclusive)

Exams are strictly in person. For any exceptions to be considered, the student should contact the Dean of Students, who must send official accommodation request to the instructor before an exam.

Lectures

Lecture 1: Introduction to Logic Design and Hardware Descriptive Languages - PDF (textbook reading: 1.1 - 1.5)

Lecture 2: Combinatorial Logic and VHDL - PDF (textbook reading: 2.1 - 2.4) (VHDL example: cir1.vhd, cir1test.vhd)

Lecture 3: VHDL Modules, Types, Operators, Libraries - PDF (textbook reading: 2.4, 2.12.1, 2.10.1) (VHDL examples: cir3_1.vhd, bit_adder.vhd, cir3_1test.vhd cir3_2.vhd, cir3_2test.vhd)

Lecture 4: VHDL Operators, Libraries, and Introduction to Sequential Logic - PDF (textbook reading: 2.10.2, 2.13, 1.6) (VHDL examples: cir4_1.vhd, cir4_1test.vhd cir4_2.vhd, cir4_2test.vhd, cir4_3.vhd, cir4_3test.vhd, cir4_4.vhd, cir4_4test.vhd)

Lecture 5: Sequential Logic Modeling and VHDL - PDF (textbook reading: 1.6, 2.5, 2.6, 2.7, 2.12.2, 2.9) (VHDL examples: cir5_1.vhd, cir5_1test.vhd)

Lecture 6: VHDL Delay and Simulation - PDF (textbook reading: 2.12.2, 2.8, 2.9) (VHDL examples: cir6_1.vhd, cir6_1test.vhd, cir6_2.vhd, cir6_2test.vhd)

Lecture 7: VHDL Simulation and Synthesis - PDF (textbook reading: 2.9, 2.11) (VHDL examples: cir6_3.vhd, cir6_3test.vhd)

Lecture 8: VHDL Synthesis - PDF (textbook reading: 2.14)

Lecture 9: VHDL Behavioral Modeling Statements - PDF (textbook reading: 2.16, 2.17, 2.18, 2.19) (VHDL examples: cir9_1.vhd, cir9_1test.vhd, cir9_2.vhd, cir9_2test.vhd, cir9_3test.vhd)

Lecture 10: Synchronous Finite State Machine Design - PDF (textbook reading: 1.7, 1.8, 2.15.1) (VHDL examples: cir10_1.vhd, cir10_1test.vhd, cir10_2.vhd, cir10_2test.vhd)

Midterm 1 Review - Midterm 1 Review PDF

Lecture 11: Synchronous FSM Designs - PDF (textbook reading: 1.7, 1.8, 2.15.1) (VHDL examples: cir11_2.vhd, cir11_2test.vhd, also look at cir10_1 and cir10_2 from lecture 10)

Lecture 12: Synchronous Design Examples - PDF (textbook reading: 4.4, 4.3, 4.8)

Lecture 13: State Machine Charts (SM Charts) - PDF (textbook reading: 5.1, 5.3)

Lecture 14: SM Charts and Microprogramming - PDF (textbook reading: 5.3, 5.5)

Lecture 15: Serial Prefix Sum Design and PA3 Handout - PDF (no textbook reading)

Lecture 16: Microprogram Design - PDF (textbook reading: 9.1)

Lecture 17: Processor Design - PDF (textbook reading: 9.1)

Lecture 18: Processor Implementation - PDF

Lecture 19: High-Level Synthesis (HLS) I - PDF (no textbook reading)

Lecture 20: High-Level Synthesis (HLS) II - PDF (no textbook reading)

Lecture 21: High-Level Synthesis (HLS) III - PDF (no textbook reading), (HLS example: neuralnet.c, neuraltest.c)

Lecture 22: Programmable Logic Devices - PDF (textbook reading: chapter 3)

Lecture 23: Verilog HDL - PDF (no textbook reading)

Homeworks (due at HuskyCT specified deadline - no late submissions will be accepted)

Homework 1: PDF, Solution PDF (due via HuskyCT on Jan 31, 2023 11:59pm EST)

Homework 2: PDF, Solution PDF (due via HuskyCT on Feb 16, 2023 11:59pm EST)

Homework 3: PDF Solution PDF (due via HuskyCT on Feb 21, 2023 11:59pm EST)

Homework 4: PDF Solution PDF (due via HuskyCT on March 27, 2023 11:59pm EST)

Homework 5: PDF Solution PDF (due via HuskyCT on April 13, 2023 11:59pm EST)

Homework 6: PDF Solution PDF (no due date)

Programming Assignments (due at HuskyCT specified deadline - no late submissions will be accepted)

Adding signals to Waveform PDF

NOTE: (1) Utilize the TA help hours, (2) Take a look at the VHDL Toolchain Guide PDF

PA 0 (due via HuskyCT on Jan 27, 2023): Complete all steps for the toolchain setup and run the lab0 with test0 testbench. Upload a single PDF of your submission in HuskyCT. PA0 Guide PDF, lab0.vhd, test0.vhd

PA 1 (due via HuskyCT on Feb 13, 2023): Design of Cascaded ALU Accumulators PA1-Handout PDF, pa1s23.zip

PA 2 (due via HuskyCT on Mar 10, 2023): 3x3 Matrix Multiplication State Machine PA2-Handout PDF, pa2s23.zip

PA 3 (due via HuskyCT on April 9, 2023 -- extended hard deadline!): Hardware Implementation of Prefix Sum PA3-Handout PDF, pa3s23.zip

PA 4 (due via HuskyCT on April 25, 2023): Two-Address Microcode Implementation of Prefix Sum PA4-Handout PDF, pa4s23.zip