----------------------------------------------------------------------------------
-- sim_example -- multiple updates to a signal
----------------------------------------------------------------------------------


library IEEE;
use IEEE.NUMERIC_BIT.ALL;

--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity signal_multiple_updates_example is
  Port ( clk : in bit;
         a : inout bit := '1';
         b : inout bit := '1';
         c : inout bit := '0');
end signal_multiple_updates_example;

architecture Behavioral of signal_multiple_updates_example is

begin

 process (clk)
 begin
  if clk'event and clk='1' then  --pos esge of clk
   a <= b;
   b <= c;
   c <= a;
   a <= c;
  end if;
 end process;

end Behavioral;