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-- ECE 3401 Spring 2024 HW5 VHDL Starter File
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity hw5_q1 is 
port(
    -- Inputs
    clk        : in std_logic;
    X0, X1, X2 : in std_logic;
    -- Outputs
    Z0, Z1, Z2 : out std_logic); 

end hw5_q1;

architecture Behavioral of hw5_q1 is 

    -- Microcode ROM table format:
    -- TEST NST Z2 Z1 Z0 
    -- xx   xx  x  x  x
    -- MSB            LSB

    type ucode_ROM is array (0 to 3) of std_logic_vector(6 downto 0);
    constant table : ucode_ROM := ( --TODO: Complete the microcode ROM table (hint: look at the above ROM format));

    -- State register and next state MUX output
    signal state      : std_logic_vector(1 downto 0) := "00";
    signal next_state : std_logic_vector(1 downto 0);
    
    -- Next state true and test bits
    signal NST, test : std_logic_vector(1 downto 0);
  
    -- Output of the test MUX
    signal test_out  : std_logic;
    
    -- Row index into the ucode ROM table
    signal table_idx : integer := 0;
    
begin
    
    -- Convert std_logic_vector --> integer
    table_idx <= -- TODO : Assign index into ROM table (hint: array indices must be an integer)
    test <= -- TODO: Extract test bits
    NST  <= -- TODO: Extract NST bits
    Z0   <= -- TODO: Extract Z0 output
    Z1   <= -- TODO: Extract Z1 output
    Z2   <= -- TODO: Extract Z2 output
    
    test_out <= -- TODO: Logic for the qualifier test MUX output 
                
    next_state <= --TODO: Logic for the next state output MUX
    
    -- TODO: Update the state on the rising edge of the clock
        
end;