----------------------------------------------------------------------------------
-- Company:				University of Connecticut
-- Engineer:			Farrukh Hijaz
-- 
-- Create Date:		10:36:58 08/30/2012 
-- Design Name:		Lab 1 Demo
-- Module Name:		demo - Behavioral 
-- Project Name: 		Fall2012_demo
-- Target Devices:	Nexys2 - Spartan 3E
-- Tool versions:		Xilinx ISE 14.2
-- Description:		Displaying text on 7-segment display
--
-- Dependencies: 
--
-- Revision: 			1.0
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demo is
    Port( 
		seg : out std_logic_vector(6 downto 0);
		an : out std_logic_vector(3 downto 0);
		btn : in std_logic;
		sw : in std_logic;
		clk : in std_logic );
end demo;

architecture Behavioral of demo is
	signal segment0 : std_logic_vector(6 downto 0);
	signal segment1 : std_logic_vector(6 downto 0);
	signal segment2 : std_logic_vector(6 downto 0);
	signal segment3 : std_logic_vector(6 downto 0);
	signal onesec_clk : std_logic;
	signal onemsec_clk : std_logic;
	signal data : std_logic_vector(15 downto 0);
	signal hex : std_logic_vector(15 downto 0);
	signal sys_rst : std_logic;
	signal dec0 : std_logic_vector(3 downto 0);
	signal dec1 : std_logic_vector(3 downto 0);
	signal dec2 : std_logic_vector(3 downto 0);
	signal dec3 : std_logic_vector(3 downto 0);
begin

	sys_rst <= btn;

 	onesec_clk_divider : entity work.clock_divider
		generic map ( divisor => 50000000 )
		port map ( clk_in => clk, reset => sys_rst, clk_out => onesec_clk );
	
 	onemsec_clk_divider : entity work.clock_divider
		generic map ( divisor => 2**16 )
		port map ( clk_in => clk, reset => sys_rst, clk_out => onemsec_clk );
	
	process(onesec_clk,sys_rst)
--		variable dec0, dec1, dec2, dec3 : std_logic_vector(3 downto 0);	
	begin
		if ( sys_rst = '1' ) then
			hex <= X"0000";
			dec0 <= "0000";
			dec1 <= "0000";
			dec2 <= "0000";
			dec3 <= "0000";		
		elsif (onesec_clk'event and onesec_clk = '1') then

			hex <= X"10af";
			dec0 <= "0001";
			dec1 <= "0111";
			dec2 <= "0010";
			dec3 <= "0100";		

			if ( sw = '1' ) then
				data <= hex;
			else
				data <= dec3 & dec2 & dec1 & dec0;
			end if;

		end if;
	end process;

	hex0 : entity work.hex2led
		port map ( segment => segment0,
				 hex => data(3 downto 0) );

	hex1 : entity work.hex2led
		port map ( segment => segment1,
				 hex => data(7 downto 4) );

	hex2 : entity work.hex2led
		port map ( segment => segment2,
				 hex => data(11 downto 8) );

	hex3 : entity work.hex2led
		port map ( segment => segment3,
				 hex => data(15 downto 12) );

	led_control : entity work.char_led_control
		port map ( clk => onemsec_clk,
				 reset => sys_rst,
				 enable => '1',
				 segment0 => segment0,
				 dp0 => '1',
			 	 segment1 => segment1,
				 dp1 => '1',
			 	 segment2 => segment2,
				 dp2 => '1',
			 	 segment3 => segment3,
				 dp3 => '1',
			 	 segment => seg,
			 	 an => an );

end Behavioral;