Welcome to ECE 3421 - VLSI Design and Simulation

Course Syllabus (updated 01/22/2013)

Final Exam: 5/9/13 from 1:00pm to 3:00pm in ITE 125

Instructor

• Professor Omer Khan
• Office: ITEB 439
• Email: khan@uconn.edu
• Office Hours: Th 1-2pm or by appointment via email

TAs

• Qingchuan Shi
  • Office: ITEB 314
  • Email: qingchuan.shi@uconn.edu
  • Office Hours: Wed 4-5pm

• Farrukh Hijaz
  • Office: ITEB 314
  • Email: farrukh.hijaz@engr.uconn.edu
  • Office Hours: Mon 12-1pm

Lectures

• Textbook: CMOS VLSI Design A Circuits and Systems Perspective, Fourth Edition
• Lecture 1: Introduction PDF
• Lecture 2: MOS Capacitors and Transistors PDF
• Lecture 3: CMOS Inverter Design PDF
• Lecture 4: CMOS Logic Delay Analysis PDF
• Lecture 5: Delay Analysis and Logic Effort PDF
• Lecture 6: Logic Effort PDF
• Lecture 7: Design with Wires PDF
• Lecture 8: CMOS Fabrication and Layout PDF
• Lecture 9: Power and Energy PDF
• Lecture 10: Low Power Design PDF
• Lecture 11: Combinatorial Logic PDF
• Lecture 12: Sequential Logic PDF
• Lecture 13: Sequential Logic - Sequencing PDF
• Lecture 14: Datapath Circuits - Adders PDF
• Lecture 15: Datapath Circuits - Multipliers, Shifters, Decoders, Multiplexors etc. PDF
• Lecture 16: Memories - ROM, SRAM PDF
• Lecture 17: Memories - SRAM PDF
• Lecture 18: Memories - DRAM, CAM, ROM, PLA PDF
• Lecture 19: Design Methodologies PDF
• Lecture 20: Logic Synthesis PDF
• Lecture 21: Physical Synthesis PDF
• Lecture 22: Verification and Testing PDF
• Lecture 23: Packaging, Power Distribution, Clocking, I/O PDF

Homeworks

• Homework 1 (due: 2/7/13 in class) PDF, HW1_solution
• Homework 2 (due: 2/19/13 in class) PDF, HW2_solution
• Homework 3 (due: 2/26/13 in class) PDF, HW3_solution
• Homework 4 (due: 3/26/13 in class) PDF, HW4_solution

Lab Assignments

• Lab 1: Design and Simulation of a CMOS Inverter (due: 2/7/13 in class) PDF
• Lab 2: Delay Analysis of a CMOS Inverter (due: 2/21/13 in class) PDF
• Lab 3: Design and Simulation of a CMOS NOR Gate (due: 3/5/13 in class) PDF
• Lab 4: Layout of a CMOS NAND Gate (due: 3/26/13 in class) PDF, LVS, SN05_Rules
• Lab 5: Power and Energy Analysis (due: 4/4/13 in class) PDF

Project

• Design a Counter (due: 5/5/13 at 11:59pm EST) PDF (last updated on 4/26/13)