Welcome to ECE 3401 / CSE 3302 - Digital Systems Design

Course Syllabus

Instructor

• Omer Khan
• Office: ITEB 447
• Email: khan@uconn.edu
• Office Hours: Wed 12pm-1pm (WebEx only); email to setup in-person meeting

TAs

• Zachary DiMeglio
• Email: zachary.dimeglio@uconn.edu
• Office Hours: Tuesdays 4-5:30pm & Fridays 12:30-2pm in building E2 307

Announcements

• Exam 2 is scheduled in-person, in-class on April 11, 2024 (lectures 9 through 17 inclusive)
• Exam 1 is scheduled in-person, in-class on Feb 22, 2024 (lectures 1 through 9 inclusive)

Lectures

• Lecture 1: Introduction to Logic Design and Hardware Descriptive Languages - PDF (textbook reading: 1.1 - 1.5)
• Lecture 2: Combinatorial Logic and VHDL - PDF (textbook reading: 2.1 - 2.4) (VHDL example: cir1.vhd, cir1test.vhd)
• Lecture 3: VHDL Modules, Types, Operators, Libraries - PDF (textbook reading: 2.4, 2.12.1, 2.10.1) (VHDL examples: cir3_1.vhd, bit_adder.vhd, cir3_1test.vhd cir3_2.vhd, cir3_2test.vhd)
• Lecture 4: VHDL Operators, Libraries, and Introduction to Sequential Logic - PDF (textbook reading: 2.10.2, 2.13, 1.6) (VHDL examples: cir4_1.vhd, cir4_1test.vhd cir4_2.vhd, cir4_2test.vhd, cir4_3.vhd, cir4_3test.vhd, cir4_4.vhd, cir4_4test.vhd)
• Lecture 5: Sequential Logic Modeling and VHDL - PDF (textbook reading: 1.6, 2.5, 2.6, 2.7, 2.12.2, 2.9) (VHDL examples: cir5_1.vhd, cir5_1test.vhd)
• Lecture 6: VHDL Delay and Simulation - PDF (textbook reading: 2.12.2, 2.8, 2.9) (VHDL examples: cir6_1.vhd, cir6_1test.vhd, cir6_2.vhd, cir6_2test.vhd)
• Lecture 7: VHDL Simulation and Synthesis - PDF (textbook reading: 2.9, 2.11) (VHDL examples: cir6_3.vhd, cir6_3test.vhd)
• Lecture 8: VHDL Synthesis - PDF (textbook reading: 2.14)
• Lecture 9: VHDL Behavioral Modeling Statements - PDF (textbook reading: 2.16, 2.17, 2.18, 2.19) (VHDL examples: cir9_1.vhd, cir9_1test.vhd, cir9_2.vhd, cir9_2test.vhd, cir9_3test.vhd)
• Midterm 1 Review - Midterm 1 Review PDF
• Lecture 10: Synchronous Finite State Machine Design - PDF (textbook reading: 1.7, 1.8, 2.15.1) (VHDL examples: cir10_1.vhd, cir10_1test.vhd, cir10_2.vhd, cir10_2test.vhd)
• Lecture 11: Synchronous FSM Designs - PDF (textbook reading: 1.7, 1.8, 2.15.1) (VHDL examples: cir11_2.vhd, cir11_2test.vhd, also look at cir10_1 and cir10_2 from lecture 10)
• Lecture 12: Synchronous Design Examples - PDF (textbook reading: 4.4, 4.3, 4.8)
• Lecture 13: State Machine Charts (SM Charts) - PDF (textbook reading: 5.1, 5.3)
• Lecture 14: SM Charts and Microprogramming - PDF (textbook reading: 5.3, 5.5)
• Lecture 15: Microprogramming - PDF (textbook reading: 5.5)
• Lecture 16: Microprogram Design - PDF (textbook reading: 9.1)
• Lecture 17: Processor Design - PDF (textbook reading: 9.1)
• Lecture 18: Processor Implementation - PDF
• Lecture 19: High-Level Synthesis (HLS) I - PDF (no textbook reading)
• Midterm 2 Review - Midterm 2 Review PDF
• Lecture 20: High-Level Synthesis (HLS) II - PDF (no textbook reading), (HLS example: neuralnet.c, neuraltest.c)
• Lecture 21: Programmable Logic Devices I - PDF (textbook reading: chapter 3)
• Lecture 22: Programmable Logic Devices II - PDF (textbook reading: chapter 3)
• Lecture 23: Verilog HDL - PDF (no textbook reading)

Homeworks (due at HuskyCT specified deadline - no late submissions will be accepted)

• Homework 1: PDF, Solution PDF (due via HuskyCT on Feb 2, 2024 11:59pm EST)
• Homework 2: PDF, Solution PDF (due via HuskyCT on Feb 13, 2024 11:59pm EST)
• Homework 3: PDF, Solution PDF (due via HuskyCT on March 8, 2024 11:59pm EST)
• Homework 4: PDF, Solution PDF (due via HuskyCT on March 29, 2024 11:59pm EST)
• Homework 5: PDF, (VHDL files: hw5_q1.vhd, hw5_q1_test.vhd , Solution PDF (due via HuskyCT on April 5, 2024 11:59pm EST)
• Homework 6: PDF, Solution PDF (due via HuskyCT on April 26, 2024 11:59pm EST)

Programming Assignments (due at HuskyCT specified deadline - no late submissions will be accepted)

• Adding signals to Waveform PDF
• NOTE: (1) Utilize the TA help hours, (2) Take a look at the VHDL Toolchain Guide (updated on Jan 22, 2024) PDF
• PA 0 (due via HuskyCT on Jan 26, 2024): Complete all steps for the toolchain setup and run the lab0 with test0 testbench. Upload a single PDF of your submission in HuskyCT. PA0 Guide PDF, lab0.vhd, test0.vhd
• PA 1 (due via HuskyCT on Feb 16, 2024): Design of Parallel ALUs with Feedback PA1-Handout PDF, pa1s24.zip
• PA 2 (due via HuskyCT on Mar 22, 2024): A Row-wise Matrix Multiplication Design PA2-Handout PDF, pa2s24.zip
• PA 3 (due via HuskyCT on April 19, 2024): Parallel Factorial Design PA4-Handout PDF, pa3s24.zip