Omer Khan is an Associate Professor of Electrical and Computer Engineering at the University of Connecticut. He holds the Castleman Term Professorship in Engineering Innovation, and serves as an Associate Director of Connecticut Advanced Computing Center (CACC). Prior to joining UConn, Khan was a Postdoctoral Research Scientist at the Massachusetts Institute of Technology. He received Ph.D. from the University of Massachusetts Amherst. Before joining academia, he designed microprocessors at leading semiconductor companies, Motorola and Intel.
We presented a Special Session on Algorithm–Hardware Co-Design for Graph Neural Networks – Video Recording
I am recruiting PhD students to work on parallel and secure computer architectures. Contact me via email.
PhD in Electrical and Computer Engineering, 2009
University of Massachusetts Amherst
BSc in Electrical and Computer Engineering, 2000
Michigan State University
My research interests can be generalized to the field of Computer Architecture and Systems. My current research deals with hardware–software mechanisms for parallelism, security, and resiliency of future parallel computer architectures. I enjoy simulating and building architecture prototypes.
Many emerging applications comprise real-time automated processing, interpretation, and intelligent decisions using large volumes of input data, while simultaneously decreasing the time necessary to arrive at a decision. The objective of this research is to explore both hardware and software parallelism challenges holistically, characterize key bottlenecks, and explore architectural methods that improve performance, lower energy, and lower programmer effort.
Computer systems have recently seen a rise of malicious exploits on processor hardware. Virtualization technologies expose hardware resources, thus requiring strong isolation and obfuscation guarantees for security. Moreover, with the advent of confidential computing, the authenticity of sensitive code execution requires fast remote attestations. This research aims to address these challenges by devising methods to secure parallel processors, while meeting the efficiency and responsiveness expectations of the system.
The focus of this reseaerch is to build architectural mechanisms and protocols that exploit application through hardware layers to co-optimize processor resiliency and efficiency.
I am the principal investigator for the NSF REU Site on Trustable Embedded Systems Security. To learn more about the research projects and highlights from past summers, visit the REU site’s official webpage.js-id-Demo