|
Omer Khan
|
I am an Associate Professor of Electrical and Computer Engineering at the University of Connecticut. Prior to joining UConn, I was a Postdoctoral Research Scientist at Massachusetts Institute of Technology with Professors Srini Devadas and Anant Agarwal. I received my Ph.D. in Electrical and Computer Engineering from the University of Massachusetts Amherst in 2009 with Professor Sandip Kundu. I also have more than seven years of industry experience designing superscalar microprocessors and multicores at leading semiconductor companies, Motorola (now NXP) and Intel.
Research (Full Publication List)
My research interests can be generalized to the field of Computer Systems and Architecture. My current research deals with hardware-algorithmic co-design mechanisms for concurrency, locality, resiliency, and security of parallel computer architectures. I enjoy simulating and building architecture prototypes.
- Parallel Computer Architecture for Domain-centric Hardware Acceleration (supported by the National Science Foundation, Semiconductor Research Corporation, and Department of Defense/Naval Research Laboratory)
- Many emerging market segments have seen resurgence of applications that comprise real-time automated processing, interpretation, and development of intelligent decisions using large volumes of input data, while simultaneously decreasing the time necessary to arrive at a decision. This research explores the domain of data analytic problems that require sensors-to-decision class of algorithms. The objective is to explore both hardware and software concurrency challenges holistically, characterize key bottlenecks, and explore architectural methods that improve performance, lower energy, and lower programmer effort.
- Secure Multicore and Accelerator Architectures (supported by the National Science Foundation, NXP Semiconductors, and Connecticut Cybersecurity Center (C^3))
- Computer systems have recently seen a rise of malicious exploits, such as Spectre, Meltdown and Foreshadow attacks on commercial processors. Traditionally, the memory and performance requirements of an application have been dealt with using explicit hardware resources, resulting in minimal sharing of resources leading to strong isolation among applications. However, with sensors-to-decision problems executing concurrently on emerging multicore and GPU machines, the memory and many other computational resources must be organized as shared resources. One of the caveat in such a system is security, where indirect attacks, such as unsafe access to memory mapped data, or information leakage across the shared software and hardware channels can lead to insecure computing substrates. This research aims to address these challenges by devising methods to secure such systems while meeting the efficiency and responsiveness expectations of the system.
- Resilient Multicore Architectures (supported by the National Science Foundation, NXP Semiconductors, UTC Institute for Advanced Systems Engineering)
- Today's designs are being shaped by the challenges of nanoscale technologies: increased power consumption, and escalating occurance of hardware faults at runtime severly hamper the functionality and performance guarantees of future computer systems. The focus of this reseaerch is on building high performance architectural mechanisms and protocols that exploit application through hardware layers to co-optimize system resiliency and efficiency.
- HeteroMap: A Runtime Performance Predictor for Efficient Processing of Graph Analytics on Heterogeneous Multi-Accelerators, ISPASS '19 Download Link
- CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores, IISWC '15 Download Link
- A Cycle-level Multithreaded Multicore Simulator for the 1000-core Era, TCAD '12, ISPASS '11 Download Link
- Current Students
- Masab Ahmad (Ph.D.)
- Hamza Omar (Ph.D.)
- Akif Rehman (M.S./Ph.D.)
- Mohsin Shan (M.S./Ph.D.)
- Former Students
- Doctoral
- Halit Dogan, Ph.D., 2018, UCONN (Intel, Massachusetts)
- Qingchuan Shi, Ph.D., 2017, UCONN (AMD, Boxborough, MA)
- Farrukh Hijaz, Ph.D., 2016, UCONN (Qualcomm, San Diego, CA)
- George Kurian, Ph.D. 2015, MIT (Google, Mountain View, CA)
- Masters
- Kartik Lakshminarasimhan, M.S. 2016, UCONN (Intel, India)
- Undergraduate
- Maia Iyer (REU student, Summer 2019)
- Brandon D'Agostino (REU student, Summer 2019)
- Adithya Nott (REU student, Summer 2017)
- Siena Biales (REU student, Summer 2016)
- Emanuel Correa (REU student, Summer 2016)
- James Palmer (REU student, Summer 2016)
- Astha Patni (REU student, Summer 2015)
- Michal Zielinski (UG student, Summer 2015)
- Matthew Seita (REU student, Summer 2014)
- Ethan Johnson (REU student, Summer 2014)
- Neil Butcher (REU student, Summer 2013)
Teaching
- ECE 6095: Advanced Digital Systems Design (Spring 2019)
- ECE 3401: Digital Systems Design (Spring 2019, Spring 2018, Spring 2017, Spring 2016, Spring 2015)
- ECE 5402/CSE 5302/CSE 4302: Computer Architecture (Fall 2017, Fall 2016, Fall 2015, Fall 2013)
- ECE 6095: Advanced Multicore Architectures (Spring 2016, Spring 2014)
- ECE 4401: Digital Design Lab (Fall 2014, Fall 2012)
- ECE 3421: VLSI Design and Simulation (Spring 2013)
Service
- Leadership Roles
- ACM Transactions on Architecture and Code Optimization, Associate Editor (as of January 2019)
- IEEE International Conference on Computer Design, Steering Committee Member (as of November 2018)
- IEEE Computer Society Integrity Chair (2019, 2018)
- Organizing Committee Member
- IEEE International Conference on Computer Design: ICCD 2018, ICCD 2017 (General Chair)
- IEEE International Conference on Computer Design: ICCD 2016 (Program Chair)
- IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems: DFT 2016 (General Chair)
- Workshop on Silicon Errors in Logic - System Effects: SELSE 2018 (Web Chair)
- IEEE International Symposium on Workload Characterization: IISWC 2016 (Workshops/Tutorials Chair)
- Guest Editor, IEEE Transactions on Emerging Topics in Computing: IEEE TETC (Special Issue/Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems)
- IEEE International Symposium on High Performance Computer Architecture: HPCA 2016 (Sponsor Chair)
- IEEE International Conference on Computer Design: ICCD 2015 (Computer Systems and Applications Track Co-Chair)
- IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems: DFT 2015 (Program Chair)
- ACM/IEEE International Symposium on Computer Architecture: ISCA 2015 (Workshop Chair)
- ACM/IEEE International Symposium on Computer Architecture: ISCA 2014 (Web Chair)
- IEEE International Conference on Computer Design: ICCD 2015 (Publication Chair), ICCD 2014 (Publication Chair), ICCD 2013 (Special Sessions Chair), ICCD 2012 (Web Chair), ICCD 2011 (Local Arrangements Co-Chair and Web Chair)
- Workshop on Computer Architecture and Operating System Co-design: CAOS 2012 (General Co-Chair)
- Program Committee Member
- IEEE International Symposium on Performance Analysis of Systems and Software: ISPASS 2019, ISPASS 2015
- IEEE International Parallel and Distributed Processing Symposium: IPDPS 2018, IPDPS 2016, IPDPS 2013
- ACM/IEEE International Symposium on Computer Architecture: ISCA 2017
- IEEE International Symposium on Workload Characterization: IISWC 2017, IISWC 2016, IISWC 2015, IISWC 2014
- IEEE/ACM International Conference on Parallel Architecture and Compilation: PACT 2016, PACT 2015
- ACM International Conference on High-Performance and Embedded Architectures and Compilers: HiPEAC 2018, HiPEAC 2017, HiPEAC 2016, HiPEAC 2015
- ACM International Conference on Supercomputing: ICS 2016, ICS 2013
- IEEE International Conference on Computer Design: ICCD 2014, ICCD 2013, ICCD 2012, ICCD 2011
- IEEE International Conference on Networking, Architecture, and Storage: NAS 2016
- IEEE International Conference on High-Performance Computing, Data and Analytics: HiPC 2017, HiPC 2016
- Boston are ARChitecture Annual Workshop: BARC 2016, BARC 2015
- IEEE International Symposium on VLSI: IVLSI 2013, ISVLSI 2012
- Others: EUC 2013, EUC 2012, TEMM 2011, EXERT 2011, CAOS 2011, UCAS 2010
- External Review Committee Member
- IEEE International Symposium on High Performance Computer Architecture: HPCA 2019, HPCA 2018, HPCA 2017, HPCA 2016, HPCA 2015
- ACM/IEEE International Symposium on Computer Architecture: ISCA 2016, ISCA 2015, ISCA 2014
- IEEE/ACM International Conference on Parallel Architecture and Compilation: PACT 2014
- IEEE/ACM International Symposium on Microarchitecture: MICRO 2017, MICRO 2016, MICRO 2015, MICRO 2014, MICRO 2012
- ACM International Conference on Supercomputing: ICS 2018
- ACM/EDAC/IEEE Design Automation Conference: DAC 2013
- Reviewer: Journal of Supercomputing, Journal of Parallel and Distributed Computing, IEEE Transactions on Computers, IEEE Transactions on Dependable and Secure Computing, IEEE Transactions on VLSI, ACM Transactions on Embedded Computing Systems, ACM Transactions on Design Automation of Electronic Systems.
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and conditions invoked by each authors' copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.