Omer Khan

Omer Khan

Professor of Computer Engineering

University of Connecticut

Biography

Omer Khan is an Associate Professor of Electrical and Computer Engineering at the University of Connecticut. He holds the Castleman Term Professorship in Engineering Innovation, and serves as an Associate Director of Connecticut Advanced Computing Center (CACC). Prior to joining UConn, Khan was a Postdoctoral Research Scientist at the Massachusetts Institute of Technology. He received Ph.D. in Electrical and Computer Engineering from the University of Massachusetts Amherst. Before joining academia, he designed microprocessors at leading semiconductor companies, Motorola and Intel.

Announcements

I am looking for PhD students to work on secure parallel architectures. Contact me via email.

Interests

  • Computer Architecture
  • Parallel Processor
  • Secure Processor

Education

  • PhD in Electrical and Computer Engineering, 2009

    University of Massachusetts Amherst

  • BSc in Electrical and Computer Engineering, 2000

    Michigan State University

Projects

NSF NRL SRC Intel ARM NXP comcast

Research Activities

My research interests can be generalized to the field of Computer Architecture and Systems. My current research deals with hardware–software mechanisms for concurrency, resiliency, and security of future parallel computer architectures. I enjoy simulating and building architecture prototypes.

Hardware Concurrency in Parallel Computer Architectures

Many emerging applications comprise real-time automated processing, interpretation, and intelligent decisions using large volumes of input data, while simultaneously decreasing the time necessary to arrive at a decision. The objective of this research is to explore both hardware and software concurrency challenges holistically, characterize key bottlenecks, and explore architectural methods that improve performance, lower energy, and lower programmer effort.

Secure Parallel Architectures

Computer systems have recently seen a rise of malicious exploits on processor hardware. Virtualization technologies expose hardware resources, thus requiring strong isolation and obfuscation guarantees for security. Moreover, with the advent of confidential computing, the authenticity of sensitive code execution requires fast remote attestations. This research aims to address these challenges by devising methods to secure parallel processors, while meeting the efficiency and responsiveness expectations of the system.

Resilient Parallel Architectures

The focus of this reseaerch is to build architectural mechanisms and protocols that exploit application through hardware layers to co-optimize processor resiliency and efficiency.

Open Source Software

  • HeteroMap: A Runtime Performance Predictor for Efficient Processing of Graph Analytics on Heterogeneous Multi-Accelerators, ISPASS'19 Download Link
  • CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores, IISWC'15 Download Link
  • A Cycle-level Multithreaded Multicore Simulator for the 1000-core Era, TCAD'12, ISPASS'11 Download Link
  • DARSIM: A parallel cycle-level NoC Simulator, MoBS'10 Download Link

Research Experiences for Undergraduates (REU)

I am the principal investigator for the NSF REU Site on Trustable Embedded Systems Security. To learn more about the research projects and highlights from past summers, visit the REU site’s official webpage

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Recent Publications

Discover relevant content by filtering all publications.
(2022). HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores. IEEE International Symposium on High-Performance Computer Architecture (HPCA).

(2022). Secure Remote Attestation with Strong Key Insulation Guarantees. CoRR.

PDF

(2021). ConNOC: A practical timing channel attack on network-on-chip hardware in a multicore processor. IEEE International Symposium on Hardware Oriented Security and Trust.

(2021). Seeds of SEED: Characterizing Enclave-level Parallelism in Secure Multicore Processors. IEEE International Symposium on Secure and Private Execution Environment Design.

DOI

Students

Current Students

  • Mohsin Shan (Ph.D.)
  • Deniz Gurevin (Ph.D.)
  • Usman Ali (Ph.D.)
  • Jared Nye (Ph.D.)
  • Rasheed Sahni (M.S./Ph.D.)
  • Salman Khaliq (M.S.)

Former Students

Doctoral

Masters

  • Brandon D’Agostino, M.S. 2021, UConn (PhD Student at Stanford University)
  • Akif Rehman, M.S. 2019, UConn (Qualcomm)
  • Kartik Lakshminarasimhan, M.S. 2016, UConn (PhD Student at Ghent University)

Undergraduates

  • Jared Nye (REU student, Summer 2021)
  • Maia Iyer (REU student, Summer 2019)
  • Brandon D’Agostino (REU student, Summer 2019, AY 2019-21)
  • Adithya Nott (REU student, Summer 2017)
  • Siena Biales (REU student, Summer 2016)
  • Emanuel Correa (REU student, Summer 2016)
  • James Palmer (REU student, Summer 2016)
  • Astha Patni (REU student, Summer 2015)
  • Michal Zielinski (UG student, Summer 2015)
  • Matthew Seita (REU student, Summer 2014)
  • Ethan Johnson (REU student, Summer 2014)
  • Neil Butcher (REU student, Summer 2013)

Teaching

Digital Systems Design

  • ECE 3401/ CSE 3302/ ECE 6095: Spring 2022, Spring 2021, Spring 2020, Spring 2019, Spring 2018, Spring 2017, Spring 2016, Spring 2015

Computer Architecture

  • ECE 5402/ CSE 5302/ CSE 4302: Fall 2021, Fall 2020, Fall 2017, Fall 2016, Fall 2015, Fall 2013

Multicore Architecture

Digital Design Lab

VLSI Design and Simulation

Service

Memberships

  • Senior Member of the IEEE
  • Member of the ACM

Leadership Roles

Organizing Committee Member

  • IEEE International Symposium on Secure and Private Execution Environment Design: SEED 2022 (General Chair)
  • IEEE International Symposium on Workload Characterization: IISWC 2021 (General Chair)
  • IEEE International Conference on Computer Design: ICCD 2021 (Conference Chair), ICCD 2020 (Conference Chair), ICCD 2018 (General Chair), ICCD 2017 (General Chair)
  • IEEE International Conference on Computer Design: ICCD 2016 (Program Chair)
  • IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems: DFT 2016 (General Chair)
  • IEEE/ACM International Symposium on Microarchitecture: MICRO 2020 (Travel Award Chair)
  • Workshop on Silicon Errors in Logic - System Effects: SELSE 2018 (Web Chair)
  • IEEE International Symposium on Workload Characterization: IISWC 2016 (Workshops/Tutorials Chair)
  • Guest Editor, IEEE Transactions on Emerging Topics in Computing: IEEE TETC (Special Issue/Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems)
  • IEEE International Symposium on High Performance Computer Architecture: HPCA 2016 (Sponsor Chair)
  • IEEE International Conference on Computer Design: ICCD 2015 (Computer Systems and Applications Track Co-Chair)
  • IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems: DFT 2015 (Program Chair)
  • ACM/IEEE International Symposium on Computer Architecture: ISCA 2015 (Workshop Chair)
  • ACM/IEEE International Symposium on Computer Architecture: ISCA 2014 (Web Chair)
  • IEEE International Conference on Computer Design: ICCD 2015 (Publication Chair), ICCD 2014 (Publication Chair), ICCD 2013 (Special Sessions Chair), ICCD 2012 (Web Chair), ICCD 2011 (Local Arrangements Co-Chair and Web Chair)
  • Workshop on Computer Architecture and Operating System Co-design: CAOS 2012 (General Co-Chair)

Program Committee Member

  • IEEE International Symposium on Secure and Private Execution Environment Design: SEED 2021
  • ACM International Conference on Supercomputing: ICS 2021, ICS 2016, ICS 2013
  • IEEE International Symposium on Performance Analysis of Systems and Software: ISPASS 2021, ISPASS 2020, ISPASS 2019, ISPASS 2015
  • IEEE International Parallel and Distributed Processing Symposium: IPDPS 2021, IPDPS 2018, IPDPS 2016, IPDPS 2013
  • IEEE/ACM International Conference on Parallel Architecture and Compilation: PACT 2020, PACT 2016, PACT 2015
  • IEEE International Symposium on High Performance Computer Architecture: HPCA 2020
  • IEEE International Symposium on Workload Characterization: IISWC 2020, IISWC 2019, IISWC 2017, IISWC 2016, IISWC 2015, IISWC 2014
  • ACM International Conference on High-Performance and Embedded Architectures and Compilers: HiPEAC 2021, HiPEAC 2020, HiPEAC 2019, HiPEAC 2018, HiPEAC 2017, HiPEAC 2016, HiPEAC 2015
  • Hardware and Architectural Support for Security and Privacy: HAPS 2020, HASP 2019, HASP 2018
  • ACM/IEEE International Symposium on Computer Architecture: ISCA 2017
  • IEEE International Conference on High-Performance Computing, Data and Analytics: HiPC 2020, HiPC 2017, HiPC 2016
  • IEEE International Conference on Networking, Architecture, and Storage: NAS 2016
  • Boston are ARChitecture Annual Workshop: BARC 2016, BARC 2015
  • IEEE International Conference on Computer Design: ICCD 2014, ICCD 2013, ICCD 2012, ICCD 2011
  • IEEE International Symposium on VLSI: IVLSI 2013, ISVLSI 2012
  • Others: EUC 2013, EUC 2012, TEMM 2011, EXERT 2011, CAOS 2011, UCAS 2010

External Review Committee Member

  • ACM/IEEE International Symposium on Computer Architecture: ISCA 2021, ISCA 2020, ISCA 2016, ISCA 2015, ISCA 2014
  • IEEE International Symposium on High Performance Computer Architecture: HPCA 2022, HPCA 2021, HPCA 2019, HPCA 2018, HPCA 2017, HPCA 2016, HPCA 2015
  • ACM International Conference on Supercomputing: ICS 2018
  • IEEE/ACM International Symposium on Microarchitecture: MICRO 2021, MICRO 2017, MICRO 2016, MICRO 2015, MICRO 2014, MICRO 2012
  • IEEE/ACM International Conference on Parallel Architecture and Compilation: PACT 2014
  • ACM/EDAC/IEEE Design Automation Conference: DAC 2013

Ad-hoc Reviewer

  • IEEE Computer Architecture Letters, IEEE Transactions on Computers, Journal of Parallel and Distributed Computing, IEEE Transactions on Dependable and Secure Computing, IEEE Transactions on VLSI, ACM Transactions on Embedded Computing Systems, ACM Transactions on Design Automation of Electronic Systems, Journal of Supercomputing.

Contact

  • khan@uconn.edu
  • 860 486 2192
  • 371 Fairfield Way, Unit 4157, Storrs, CT 06269
  • Enter the ITE Building and take the stairs to Office 447 on Floor 4