Research Activities
My research interests can be generalized to the field of Computer Architecture and Systems.
My current research deals with hardware–software mechanisms for concurrency, resiliency, and security of future parallel computer architectures.
I enjoy simulating and building architecture prototypes.
Hardware Concurrency in Parallel Computer Architectures
Many emerging applications comprise real-time automated processing, interpretation, and intelligent decisions using large volumes of input data, while simultaneously decreasing the time necessary to arrive at a decision. The objective of this research is to explore both hardware and software concurrency challenges holistically, characterize key bottlenecks, and explore architectural methods that improve performance, lower energy, and lower programmer effort.
- Architecture Support for Parallelism –
HPCA'22,
CAL'21,
ICS'20,
Micro'20,
TACO'19,
IPDPS'17
- Accelerating Graph Processing –
HPEC'21,
ISPASS'19,
IPDPS'18,
Micro'17,
IISWC'15
- Locality-Aware Cache Coherence –
ISCA'13,
HPCA'14,
PACT'15,
TACO'16,
CAL'11
- Library Cache Coherence –
MIT-TR'11
- The Execution Migration Machine –
COMPUTER'15,
CAL'14,
NOCS'11
- Asymmetric Multicores –
PACT'11,
PACT'12,
GLSVLSI'10
- Architecture for High Performance Power Electronics –
RTSS'11,
DATE'13
Secure Parallel Architectures
Computer systems have recently seen a rise of malicious exploits on processor hardware. Virtualization technologies expose hardware resources, thus requiring strong isolation and obfuscation guarantees for security. Moreover, with the advent of confidential computing, the authenticity of sensitive code execution requires fast remote attestations. This research aims to address these challenges by devising methods to secure parallel processors, while meeting the efficiency and responsiveness expectations of the system.
- Secure Processor –
Arxiv'22,
SEED'21,
HOST'21,
HPEC'21,
HPCA'20,
TC'20,
CAL'18,
BARC'16,
HPCA'14
- Oblivious RAM –
ICCD'18,
arXiv'17
- Hardware Trojans –
TDSC'19
- Memory Safety –
HASP'15,
ICCD'15
Resilient Parallel Architectures
The focus of this reseaerch is to build architectural mechanisms and protocols that exploit application through hardware layers to co-optimize processor resiliency and efficiency.
- Resilient Processor –
TACO'21,
TECS'18,
CAL'15,
COMPUTER'13,
ICCD'17,
TC'10,
TDSC'11,
ITC'10,
DATE'09,
DATE'09
- Near-Threshold Computing –
TACO'14,
WNTC'14
- Multicore Thermal Management –
HiPEAC'09,
DATE'09,
ICCAD'08
Open Source Software
- HeteroMap: A Runtime Performance Predictor for Efficient Processing of Graph Analytics on Heterogeneous Multi-Accelerators, ISPASS'19
Download Link
- CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores, IISWC'15
Download Link
- A Cycle-level Multithreaded Multicore Simulator for the 1000-core Era, TCAD'12, ISPASS'11
Download Link
- DARSIM: A parallel cycle-level NoC Simulator, MoBS'10
Download Link
Research Experiences for Undergraduates (REU)
I am the principal investigator for the NSF REU Site on Trustable Embedded Systems Security. To learn more about the research projects and highlights from past summers, visit the
REU site’s official webpage
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