Publications

D. Gurevin, M. Shan, S. Huang, MD. Hasan, C. Ding, O. Khan (2024). PruneGNN: An Optimized Algorithm-Hardware Framework for Graph Neural Network Pruning. IEEE International Symposium on High-Performance Computer Architecture (HPCA).

H. Peng, X. Xie, K. Shivdikar S. Huang, MD. Hasan, J. Zhao, S. Huang, O. Khan, D. Kaeli, C. Ding (2024). MaxK-GNN: Towards Theoretical Speed Limits for Accelerating Graph Neural Networks Training. ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).

Z. DiMeglio, J. Bustami, D. Gurevin, C. Jin, M. van Dijk, O. Khan (2024). Masked Memory Primitive for Key Insulated Schemes. IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Deniz Gurevin, Caiwen Ding, Omer Khan (2024). Exploiting Intrinsic Redundancies in Dynamic Graph Neural Networks for Processing Efficiency. IEEE Computer Architecture Letters.

M. Shan, D. Gurevin, J. Nye, C. Ding, O. Khan (2023). MergePath-SpMM: Parallel Sparse Matrix-Matrix Algorithm for Graph Neural Network Acceleration. 2023 IEEE International Symposium on Performance Analysis of Systems and Software.

U. Ali, A. R. Sahni, O. Khan (2023). Characterization of Timing-Based Software Side-Channel Attacks and Mitigations on Network-on-Chip Hardware. ACM Journal on Emerging Technologies in Computing Systems.

A. R. Sahni, H. Omar, U. Ali, O. Khan (2023). ASM: An Adaptive Secure Multicore for Co-Located Mutually Distrusting Processes. ACM Trans. Archit. Code Optim..

Deniz Gurevin, Chenglu Jin, Phuong Nguyen, Omer Khan, Marten van Dijk (2023). Secure Remote Attestation with Strong Key Insulation Guarantees. IEEE Transactions on Computers.

X. Xie, H. Peng, A. Hasan, S. Huang, J. Zhao, H. Fang, W. Zhang, T. Geng, O. Khan, C. Ding (2023). Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks. 2023 IEEE/ACM International Conference On Computer Aided Design.

Z. Hu, J. Li, Z Pan, S Zhou, L. Yang, C. Ding, O. Khan, T. Geng, W. Jiang (2022). On the Design of Quantum Graph Convolutional Neural Network in the NISQ-Era and Beyond. 2022 IEEE International Conference on Computer Design.

Y. Luo, P. Behnam, K. Thorat, Z. Liu, H. Peng, S. Huang, S. Zhou, O Khan, A. Tumanov, C. Ding, T. Geng (2022). CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM. 2022 IEEE International Conference on Computer Design.

H. Peng, D. Gurevin, S. Huang, T. Geng, W. Jiang, O Khan, C. Ding (2022). Towards Sparsification of Graph Neural Networks. 2022 IEEE International Conference on Computer Design.

D. Gurevin, M. Shan, T. Geng, W. Jiang, C. Ding, O Khan (2022). Towards Real-time Temporal Graph Learning. 2022 IEEE International Conference on Computer Design.

J. Nye, O. Khan (2022). SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors. IEEE Computer Architecture Letters.

Deniz Gurevin, Chenglu Jin, Phuong Ha Nguyen, Omer Khan, Marten van Dijk (2022). Secure Remote Attestation with Strong Key Insulation Guarantees. CoRR.

U. Ali, A. R. Sahni, O. Khan (2022). Protecting On-Chip Data Access Against Timing-Based Side-Channel Attacks on Multicores. 2022 IEEE International Symposium on Secure and Private Execution Environment Design.

U. Ali, O. Khan (2022). MultiCon: An Efficient, Fast Timing-based Side Channel Attack that Exploits Multiple Shared Hardware Channels in Shared Memory Multicores. 2022 IEEE International Conference on Computer Design.

M. Shan, O. Khan (2022). HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores. IEEE International Symposium on High-Performance Computer Architecture (HPCA).

U. Ali, S. Khaliq, O. Khan (2022). Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardware. IEEE International Symposium on Quality Electronic Design (ISQED).

Hamza Omar, Omer Khan (2021). PRISM: Strong Hardware Isolation-Based Soft-Error Resilient Multicore Architecture with High Performance and Availability at Low Hardware Overheads. ACM Trans. Archit. Code Optim..

B. D'Agostino, O. Khan (2021). Seeds of SEED: Characterizing Enclave-level Parallelism in Secure Multicore Processors. IEEE International Symposium on Secure and Private Execution Environment Design.

U. Ali, O. Khan (2021). ConNOC: A practical timing channel attack on network-on-chip hardware in a multicore processor. IEEE International Symposium on Hardware Oriented Security and Trust.

Marten van Dijk, Deniz Gurevin, Chenglu Jin, Omer Khan, Phuong Ha Nguyen (2021). Bilinear Map Based One-Time Signature Scheme with Secret Key Exposure.

Marten van Dijk, Deniz Gurevin, Chenglu Jin, Omer Khan, Phuong Ha Nguyen (2021). Autonomous Secure Remote Attestation even when all Used and to be Used Digital Keys Leak.

D. Gurevin, C. Michael, O. Khan (2021). An Efficient Algorithm for the Construction of Dynamically Updating Trajectory Networks. IEEE Conference on High Performance Extreme Computing.

M. Shan, O. Khan (2021). Accelerating Concurrent Priority Scheduling using Adaptive in-Hardware Task Distribution in Multicores. IEEE Computer Architecture Letters.

Akif Rehman, Masab Ahmad, Omer Khan (2021). A performance predictor for implementation selection of parallelized static and temporal graph algorithms. Concurrency and Computation: Practice and Experience.

Hamza Omar, Brandon D'Agostino, Omer Khan (2020). OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks. IEEE Transactions on Computers.

Hamza Omar, Omer Khan (2020). IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications. IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, San Diego, CA, USA, February 22-26, 2020.

Masab Ahmad, Halit Dogan, José A. Joao, Omer Khan (2020). In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores. IEEE Micro.

Akif Rehman, Masab Ahmad, Omer Khan (2020). Exploring accelerator and parallel graph algorithmic choices for temporal graphs. PMAM@PPoPP ‘20: Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores colocated with the 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, San Diego, California, USA, February 22, 2020.

Masab Ahmad, Mohsin Shan, Akif Rehman, Omer Khan (2020). Accelerating Relax-Ordered Task-Parallel Workloads Using Multi-Level Dependency Checking. Proceedings of the 34th ACM International Conference on Supercomputing.

Masab Ahmad, Mohsin Shan, Akif Rehman, Omer Khan (2019). POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms. 28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019, Seattle, WA, USA, September 23-26, 2019.

Hamza Omar, Omer Khan (2019). IRONHIDE: A Secure Multicore Architecture that Leverages Hardware Isolation Against Microarchitecture State Attacks. CoRR.

Masab Ahmad, Halit Dogan, Christopher J. Michael, Omer Khan (2019). HeteroMap: A Runtime Performance Predictor for Efficient Processing of Graph Analytics on Heterogeneous Multi-Accelerators. IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2019, Madison, WI, USA, March 24-26, 2019.

Ozgur Sinanoglu, Omer Khan (2019). Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design. IEEE Trans. Emerg. Top. Comput..

Syed Kamran Haider, Chenglu Jin, Masab Ahmad, Devu Manikantan Shila, Omer Khan, Marten van Dijk (2019). Advancing the State-of-the-Art in Hardware Trojans Detection. IEEE Trans. Dependable Secur. Comput..

Halit Dogan, Masab Ahmad, Brian Kahne, Omer Khan (2019). Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale. TACO.

Halit Dogan, Omer Khan (2018). Utilizing Moving Compute to Data Model to Improve Scaling of Graph and Machine Learning Algorithms in QUARQ Multicore Architecture at 1000-cores Scale. 2018 SRC TECHCON.

Masab Ahmad, Halit Dogan, Fabio Checconi, Xinyu Que, Daniele Buono, Omer Khan (2018). Software-Hardware Managed Last-level Cache Allocation Scheme for Large-Scale NVRAM-Based Multicores Executing Parallel Data Analytics Applications. 2018 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2018, Vancouver, BC, Canada, May 21-25, 2018.

Hamza Omar, Halit Dogan, Brian Kahne, Omer Khan (2018). Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications. IEEE Comput. Archit. Lett..

Maria K. Michael, Salvatore Pontarelli, Omer Khan (2018). Guest Editorial: Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology. IEEE Trans. Emerg. Top. Comput..

Hamza Omar, Qingchuan Shi, Masab Ahmad, Halit Dogan, Omer Khan (2018). Declarative Resilience: A Holistic Soft-Error Resilient Multicore Architecture that Trades off Program Accuracy for Efficiency. ACM Trans. Embedded Comput. Syst..

Hamza Omar, Syed Kamran Haider, Ling Ren, Marten van Dijk, Omer Khan (2018). Breaking the Oblivious-RAM Bandwidth Wall. 36th IEEE International Conference on Computer Design, ICCD 2018, Orlando, FL, USA, October 7-10, 2018.

Halit Dogan, Masab Ahmad, José A. Joao, Omer Khan (2018). Accelerating Synchronization in Graph Analytics Using Moving Compute to Data Model on Tilera TILE-Gx72. 36th IEEE International Conference on Computer Design, ICCD 2018, Orlando, FL, USA, October 7-10, 2018.

Masab Ahmad, Halit Dogan, Omer Khan (2018). A Temporally Reconfigurable Multi-Accelerator Parallel Architecture for Reuse and Throughput Oriented Computing. 2018 SRC TECHCON.

Qingchuan Shi, Hamza Omar, Omer Khan (2017). Towards Resilient yet Efficient Parallel Execution of Convolutional Neural Networks. 2017 Boston area ARChitecture Annual Workshop (BARC).

Masab Ahmad, Omer Khan (2017). Situationally Adaptive Scheduling of Graph Algorithms on Single-Chip Parallel Machines. 2017 Boston area ARChitecture Annual Workshop (BARC).

Syed Kamran Haider, Omer Khan, Marten van Dijk (2017). Revisiting Definitional Foundations of Oblivious RAM for Secure Processor Implementations. CoRR.

Halit Dogan, Brian Kahne, Omer Khan (2017). QUARQ: A Novel General Purpose Multicore Architecture for Cognitive Computing. 2017 SRC TECHCON.

Hamza Omar, Masab Ahmad, Omer Khan (2017). GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph Algorithms. 2017 IEEE International Conference on Computer Design, ICCD 2017, Boston, MA, USA, November 5-8, 2017.

Qingchuan Shi, Hamza Omar, Omer Khan (2017). Exploiting the Tradeoff between Program Accuracy and Soft-error Resiliency Overhead for Machine Learning Workloads. CoRR (appeared in IEEE Workshop on Silicon Errors in Logic - System Effects).

Masab Ahmad, Omer Khan (2017). Exploiting Heterogeneous Parallel Accelerators to Improve Performance in Graph Analytics. 2017 SRC TECHCON. Best In Session Award.

Masab Ahmad, Christopher J. Michael, Omer Khan (2017). Efficient Situational Scheduling of Graph Workloads on Single-Chip Multicores and GPUs. IEEE Micro.

Halit Dogan, Farrukh Hijaz, Masab Ahmad, Brian Kahne, Peter Wilson, Omer Khan (2017). Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging. 2017 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2017, Orlando, FL, USA, May 29 - June 2, 2017.

Qingchuan Shi, Kartik Lakshminarashimhan, Christopher Noll, Eelco Scholte, Omer Khan (2016). A Lightweight Spatio-Temporally Partitioned Multicore Architecture for Concurrent Execution of Safety Critical Workloads. SAE Technical Paper.

Masab Ahmad, Omer Khan (2016). Tradeoffs in Secure Accelerator Designs. 2016 Boston area ARChitecture Annual Workshop (BARC).

Masab Ahmad, Omer Khan (2016). OGAPI Oblivious Graph Processing in Multicores. 2016 Boston area ARChitecture Annual Workshop (BARC).

Farrukh Hijaz, Qingchuan Shi, George Kurian, Srinivas Devadas, Omer Khan (2016). Locality-aware data replication in the last-level cache for large scale multicores. The Journal of Supercomputing.

Qingchuan Shi, George Kurian, Farrukh Hijaz, Srinivas Devadas, Omer Khan (2016). LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies. ACM Transactions on Architecture and Code Optimization (TACO) – Presentation at 2017 International Conference on High-Performance Embedded Architectures and Compilers, (HiPEAC).

Masab Ahmad, Omer Khan (2016). GPU concurrency choices in graph analytics. 2016 IEEE International Symposium on Workload Characterization, IISWC 2016, Providence, RI, USA, September 25-27, 2016.

Omer Khan, Maria K. Michael, Antonio Miele, Qiaoyan Yu (2016). Foreword. 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016, Storrs, CT, USA, September 19-20, 2016.

Sandip Kundu, Omer Khan (2016). Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores. 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016.

Qingchuan Shi, Omer Khan (2016). A Case for Deploying Multicores in Cyberphysical Embedded Systems. 2016 Boston area ARChitecture Annual Workshop (BARC).

Masab Ahmad, Chris J. Michael, Omer Khan (2016). A Case for a Situationally Adaptive Many-core Execution Model for Cognitive Computing Workloads. ASPLOS 2016 International Workshop on Cognitive Architectures, (CogArch).

Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas (2015). The Execution Migration Machine: Directoryless Shared-Memory Architecture. IEEE Computer.

George Kurian, Qingchuan Shi, Srinivas Devadas, Omer Khan (2015). OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access. 2015 International Conference on Parallel Architectures and Compilation, PACT 2015, San Francisco, CA, USA, October 18-21, 2015.

Omer Khan (2015). Many-core Architecture Characterization of the Path-Planning Workload. ASPLOS 2015 International Workshop on Cognitive Architectures, (CogArch).

Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk (2015). M-MAP: Multi-factor memory authentication for secure embedded processors. 33rd IEEE International Conference on Computer Design, ICCD 2015, New York City, NY, USA, October 18-21, 2015.

Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk (2015). M-MAP: Multi-Factor Memory Authentication for Secure Embedded Processors. IACR Cryptol. ePrint Arch..

Masab Ahmad, Syed Kamran Haider, Farrukh Hijaz, Marten van Dijk, Omer Khan (2015). Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads. Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, HASP@ISCA 2015, Portland, OR, USA, June 14, 2015.

Masab Ahmad, Kartik Lakshminarasimhan, Omer Khan (2015). Efficient parallelization of path planning workload on single-chip shared-memory multicores. 2015 IEEE High Performance Extreme Computing Conference, HPEC 2015, Waltham, MA, USA, September 15-17, 2015.

Farrukh Hijaz, Brian Kahne, Peter Wilson, Omer Khan (2015). Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication. 10th IEEE International Conference on Networking, Architecture and Storage, NAS 2015, Boston, MA, USA, August 6-7, 2015.

Masab Ahmad, Farrukh Hijaz, Qingchuan Shi, Omer Khan (2015). CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores. 2015 IEEE International Symposium on Workload Characterization, IISWC 2015, Atlanta, GA, USA, October 4-6, 2015. Best Paper Nominee.

Farrukh Hijaz, Brian Kahne, Peter Wilson, Omer Khan (2015). Accelerating Communication in Single-chip Shared Memory Many-core Processors. 2015 Boston area ARChitecture Annual Workshop (BARC).

Qingchuan Shi, Henry Hoffmann, Omer Khan (2015). A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads. IEEE Comput. Archit. Lett..

Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas (2014). Thread Migration Prediction for Distributed Shared Caches. IEEE Comput. Archit. Lett..

Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Marten van Dijk, Omer Khan, Srinivas Devadas (2014). Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs. 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014.

Farrukh Hijaz, Omer Khan (2014). Rethinking Last-Level Cache Management for Multicores Operating at Near-Threshold Voltages. ISCA 2014 International Workshop on Near-threshold Computing, (WNTC).

Farrukh Hijaz, Omer Khan (2014). NUCA-L1: A Non-Uniform Access Latency Level-1 Cache Architecture for Multicores Operating at Near-Threshold Voltages. TACO.

George Kurian, Srinivas Devadas, Omer Khan (2014). Locality-aware data replication in the Last-Level Cache. 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014.

Syed Kamran Haider, Chenglu Jin, Masab Ahmad, Devu Manikantan Shila, Omer Khan, Marten van Dijk (2014). HaTCh: Hardware Trojan Catcher. IACR Cryptol. ePrint Arch..

Srinivas Devadas, Omer Khan, Mieszko Lis, Keun Sup Shim, Myong Hyon Cho (2014). EXECUTION MIGRATION. United States Patent No. 8904154.

Omer Khan, Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Srinivas Devadas (2014). EM2: A Scalable Shared Memory Architecture for Large-Scale Multicores. Multicore Technology: Architecture, Reconfiguration and Modeling.

Qingchuan Shi, Farrukh Hijaz, Omer Khan (2013). Towards efficient dynamic data placement in NoC-based multicores. 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013.

Qingchuan Shi, Omer Khan (2013). Toward Holistic Soft-Error-Resilient Shared-Memory Multicores. IEEE Computer.

George Kurian, Omer Khan, Srinivas Devadas (2013). The locality-aware adaptive cache coherence protocol. The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013.

Michel A. Kinsy, Ivan Celanovic, Omer Khan, Srinivas Devadas (2013). MARTHA: architecture for control and emulation of power electronics and smart grid systems. Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013.

Farrukh Hijaz, Qingchuan Shi, Omer Khan (2013). A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages. 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013.

Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas (2013). A framework to accelerate sequential programs on homogeneous multicores. 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013.

Farrukh Hijaz, Qingchuan Shi, Omer Khan (2012). Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores. 45th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2012, Workshops Proceedings, Vancouver, BC, Canada, December 1-5, 2012.

Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas (2012). Judicious Thread Migration When Accessing Distributed Shared Caches. HiPEAC Workshop on Computer Architecture and Operating System Co-design (CAOS).

Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas (2012). HORNET: A Cycle-Level Multicore Simulator. IEEE Trans. on CAD of Integrated Circuits and Systems.

Omer Khan, Sandip Kundu (2012). Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime. IET Circuits, Devices & Systems.

Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas (2012). A low-overhead dynamic optimization framework for multicores. International Conference on Parallel Architectures and Compilation Techniques, PACT ‘12, Minneapolis, MN, USA - September 19 - 23, 2012.

George Kurian, Omer Khan, Srinivas Devadas (2012). A Case for Fine-Grain Adaptive Cache Coherence. MIT CSAIL Technical Report (MIT-CSAIL-TR-2012-012).

Michel A. Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola L. Celanovic, Srinivas Devadas (2011). Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems. Proceedings of the 32nd IEEE Real-Time Systems Symposium, RTSS 2011, Vienna, Austria, November 29 - December 2, 2011.

Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Omer Khan, Srinivas Devadas (2011). System-level Optimizations for Memory Access in the Execution Migration Machine (EM2). HiPEAC Workshop on Computer Architecture and Operating System Co-design (CAOS).

Mieszko Lis, Keun Sup Shim, Omer Khan, Srinivas Devadas (2011). Shared Memory via Execution Migration. Ideas and Perspectives Session at International Conference on Architectural Support for Programming Languages and Operating Systems, (ASPLOS).

Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas (2011). Scalable, accurate multicore simulation in the 1000-core era. IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2011, 10-12 April, 2011, Austin, TX, USA.

Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan (2011). Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. 2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011, Galveston, TX, USA, October 10-14, 2011.

Omer Khan, Sandip Kundu (2011). Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. Trans. HiPEAC.

Keun Sup Shim, Myong Hyon Cho, Mieszko Lis, Omer Khan, Srinivas Devadas (2011). Library Cache Coherence. MIT CSAIL Technical Report (MIT-CSAIL-TR-2011-027).

Omer Khan, Sandip Kundu (2011). Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. IEEE Trans. Dependable Secur. Comput..

Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Omer Khan, Srinivas Devadas (2011). DIRECTORYLESS SHARED MEMORY COHERENCE USING EXECUTION MIGRATION. Parallel and distributed computing and systems. Best Paper Award at PDCS 2011.

Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas (2011). Deadlock-free fine-grained thread migration. NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011. Best Paper Award.

Omer Khan, Mieszko Lis, Yildiz Sinangil, Srinivas Devadas (2011). DCC: A Dependable Cache Coherence Multicore Architecture. IEEE Computer Architecture Letters. Presented at Best Papers from CAL Session at HPCA 2012.

Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Christopher W. Fletcher, Michel A. Kinsy, Ilia A. Lebedev, Omer Khan, Srinivas Devadas (2011). Brief announcement: distributed shared memory based on computation migration. SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, San Jose, CA, USA, June 4-6, 2011 (Co-located with FCRC 2011).

Omer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas (2011). ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores. IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011.

Omer Khan, Sandip Kundu (2010). Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. IEEE Trans. Computers.

Rance Rodrigues, Sandip Kundu, Omer Khan (2010). Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010.

Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Omer Khan, Srinivas Devadas (2010). Scalable directoryless shared memory coherence using execution migration. MIT CSAIL Technical Report (MIT-CSAIL-TR-2010-053).

Carl Beckmann, Omer Khan, Sailashri Parthasarathy, Alexey Klimkin, Mohit Gambhir, Brian Slechta, Krishna Rangan (2010). Multithreaded Simulation to Increase Performance Modeling Throughput on Large Compute Grids. ASPLOS Exascale Evaluation and Research Techniques Workshop (EXERT).

Omer Khan, Mieszko Lis, Srinivas Devadas (2010). Instruction-Level Execution Migration. MIT CSAIL Technical Report (MIT-CSAIL-TR-2010-019).

Mieszko Lis, Omer Khan, Srinivas Devadas (2010). EM2: A Scalable Shared-Memory Multicore Architecture. MIT CSAIL Technical Report (MIT-CSAIL-TR-2010-030).

Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Pengju Ren, Omer Khan, Srinivas Devadas (2010). DARSIM: A parallel cycle-level NoC Simulator. ISCA International Workshop on Modeling, Benchmarking and Simulation (MoBS).

Omer Khan, Sandip Kundu (2010). A self-adaptive scheduler for asymmetric multi-cores. Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2010, Providence, Rhode Island, USA, May 16-18 2010.

Omer Khan, Sandip Kundu (2010). A model to exploit power-performance efficiency in superscalar processors via structure resizing. Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2010, Providence, Rhode Island, USA, May 16-18 2010.

Omer Khan, Sandip Kundu, Krishna Rangan (2009). Run-Time Reconfiguration for Performance and Power Optimizations in Asymmetric Chip Multiprocessors. HiPEAC Workshop on Reconfigurable Computing (WRC).

Omer Khan, Sandip Kundu (2009). Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings.

Abhisek Pan, Omer Khan, Sandip Kundu (2009). Improving yield and reliability of chip multiprocessors. Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009.

Omer Khan, Sandip Kundu (2009). Hardware/software co-design architecture for thermal management of chip multiprocessors. Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009.

Omer Khan, Sandip Kundu (2009). A self-adaptive system architecture to address transistor aging. Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009.

Omer Khan (2009). A Hardware/Software Co-Design Architecture for Thermal, Power, and Reliability Management in Chip Multiprocessors.

Omer Khan, Sandip Kundu (2008). Automatic Adjustment of System Performance to Mitigate Device Aging via a Co-designed Virtual Machine. MICRO-41 Workshop on Dependable Architectures, (WDA).

Omer Khan, Sandip Kundu (2008). A framework for predictive dynamic temperature management of microprocessor systems. 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008.